

`include "defines.v"

//----------------------------------------------------------------
//Module Name : data_conf.v
//Description of module:
//instration fetch 
//----------------------------------------------------------------
//Designer:	Tang Pengyu
//Date: 2021/09/29/16:28	  
//----------------------------------------------------------------
module	data_conf(
//本级
	input	i_id_rs1_r_ena,				//本级rs1_ena源操作数1
	input	[4:0]	i_id_rs1_r_addr,	//本级rs1_addr源操作数1
	input	[63:0]	i_id_op1,
	input	i_id_rs2_r_ena,				//本级rs2_ena源操作数2
	input	[4:0]	i_id_rs2_r_addr,	//本级rs2_addr源操作数2
	input	[63:0]	i_id_op2,
//上一级
	input	o_id_rd_w_ena,				//上一级rd_ena
	input	[4:0]	o_id_rd_w_addr,		//上一级rd_w_addr
	input	[63:0]	i_exe_data,			//上一级执行结果
	input	[1:0]	o_ctrlid_wb_sel,	//上一级wb_sel
	input	[63:0]	o_ifif_pc_out,		//上一级pc_out
	input	i_csrunit_csr_r_ena,
	input	[63:0]	csr_r_data_unit,

//上两级
	input	o_idid_rd_w_ena,			//上两级rd_w_ena
	input	[4:0]	o_idid_rd_w_addr,	//上两级rd_w_addr
	input	[63:0]	i_exeexe_data,		//上两级执行结果
	input	[1:0]	o_ctrlidctrlid_wb_sel,	//上两级wb_sel
	input	[63:0]	o_ififif_pc_out,		//上两级pc_out
	input	o_csrunit_csr_r_ena,
	input	[63:0]	o_csrunit_csr_r_data,
	
//上三级
	input	o_ididid_rd_w_ena,			//上三级rd_w_ena
	input	[4:0]	o_ididid_rd_w_addr,
	input	[63:0]	o_exeexe_data,
	input	[1:0]	o_ctrlidctrlidctrlid_wb_sel,
	input	[63:0]	o_ifififif_pc_out,
	input	[63:0]	o_lspro_axi_ld_data,
	input	o_csrunitcsrunit_csr_r_ena,
	input	[63:0]	o_csrunitcsrunit_csr_r_data,
	
//输出判断后的源操作数
	output	[63:0]	conflict_op1,
	output	[63:0]	conflict_op2
);
wire	[63:0]	data_back1;
assign	data_back1 = (o_ctrlid_wb_sel == 2'b00) ? 
				(i_csrunit_csr_r_ena ? csr_r_data_unit : i_exe_data) : 
				 (o_ctrlid_wb_sel == 2'b01) ? (o_ifif_pc_out + 4) : 
				 64'd0;
wire	[63:0]	data_back2;
assign	data_back2 = (o_ctrlidctrlid_wb_sel == 2'b00) ? 
				(o_csrunit_csr_r_ena ? o_csrunit_csr_r_data : i_exeexe_data) : 
				 (o_ctrlidctrlid_wb_sel == 2'b01) ? (o_ififif_pc_out + 4) : 
				 64'd0;
wire	[63:0]	data_back3;
assign	data_back3 = (o_ctrlidctrlidctrlid_wb_sel == 2'b00) ? 
				(o_csrunitcsrunit_csr_r_ena ? o_csrunitcsrunit_csr_r_data : o_exeexe_data) : 
				 (o_ctrlidctrlidctrlid_wb_sel == 2'b01) ? (o_ifififif_pc_out + 4) : 
				 (o_ctrlidctrlidctrlid_wb_sel == 2'b10) ? o_lspro_axi_ld_data : 64'd0;

wire	[4:0]	rs1_sel;
assign	rs1_sel = ({5{i_id_rs1_r_ena}} & i_id_rs1_r_addr);
wire	[4:0]	rs2_sel;				 
assign	rs2_sel = ({5{i_id_rs2_r_ena}} & i_id_rs2_r_addr);

wire	[4:0]	back1_rd_sel;
assign	back1_rd_sel = ({5{o_id_rd_w_ena}} & o_id_rd_w_addr);
wire	[4:0]	back2_rd_sel;
assign	back2_rd_sel = ({5{o_idid_rd_w_ena}} & o_idid_rd_w_addr);
wire	[4:0]	back3_rd_sel;
assign	back3_rd_sel = ({5{o_ididid_rd_w_ena}} & o_ididid_rd_w_addr);

wire	rs1_back1;
assign	rs1_back1 = (rs1_sel == 5'b00000) ? 1'b0 :
					(rs1_sel == back1_rd_sel) ? 1'b1 : 1'b0;
wire	rs1_back2;
assign	rs1_back2 = (rs1_sel == 5'b00000) ? 1'b0 :
					(rs1_sel == back2_rd_sel) ? 1'b1 : 1'b0;
wire	rs2_back1;
assign	rs2_back1 = (rs2_sel == 5'b00000) ? 1'b0 :
					(rs2_sel == back1_rd_sel) ? 1'b1 : 1'b0;
wire	rs2_back2;
assign	rs2_back2 = (rs2_sel == 5'b00000) ? 1'b0 :
					(rs2_sel == back2_rd_sel) ? 1'b1 : 1'b0;

wire	rs1_back3;
assign	rs1_back3 = (rs1_sel == 5'b00000) ? 1'b0 :
					(rs1_sel == back3_rd_sel) ? 1'b1 : 1'b0;
wire	rs2_back3;
assign	rs2_back3 = (rs2_sel == 5'b00000) ? 1'b0 :
					(rs2_sel == back3_rd_sel) ? 1'b1 : 1'b0;					

assign	conflict_op1 = rs1_back1 ? data_back1 :
						rs1_back2 ? data_back2 : 
						rs1_back3 ? data_back3 : i_id_op1;
assign	conflict_op2 = rs2_back1 ? data_back1 :
						rs2_back2 ? data_back2 : 
						rs2_back3 ? data_back3 : i_id_op2;
						
endmodule